1. Field of the Invention
The present invention relates to an integrated circuit which forms a circuit for supplying the reference level of a master slice large-scale integration (LSI) circuit which outputs the reference level of an emitter-coupled logic (ECL) circuit
2. Description of the Prior Art
Due to the progress made regarding digital circuit techniques, a digital circuit is required to have a rapid process speed. To effect such a rapid process speed, an ECL circuit is usually utilized. In accordance with semiconductor integrated-circuit techniques, a master slice of an ECL circuit is used in practice. In this ECL master slice, a rapid process speed is possible, and the ECL master slice can be formed so that it has small dimensions.
For the purpose of judging whether the input signal is a high (H) level or a low (L) level according to the voltage value, an ECL circuit requires a reference voltage. It also requires an electric source for driving it. Therefore, an ECL circuit has a bias circuit which generates a reference voltage and an electric source for driving the ECL circuit.
Conventionally, a bias circuit of an ECL circuit in a master slice LSI circuit is arranged in each cell and the reference voltage and the driving bias current are supplied to a gate circuit in each cell.
In another conventional construction, outer cells, which are coupled to the outer part of the LSI circuit, and inner cells, which carry out a logic process in the LSI circuit, are separated. These cells have the bias circuit mentioned above. The outer cells provide a bias circuit for outputting the reference voltage level so as to maintain the logic level of the outer part, and the inner cells have a simple bias circuit because they are not connected to the outer circuit.
In the conventional system mentioned above, the reference voltage is supplied from one bias circuit to a plurality of gates, for example, four gates. This supply system provides a plurality of reference voltage-generating circuits, and much electric power is required.
Ideally, it is desired to supply the voltage from one bias circuit to all of the gates on the chip. However, because of the driving capacity of the bias circuit, etc., the voltage is supplied from one bias circuit to a plurality of gates, for example, four gates, as mentioned above.
In the conventional master slice LSI circuit in which, prior to the last wiring process, the necessary elements for many gates are formed on a semiconductor substrate, the power of the internal gate cannot be selected during the last wiring process. Therefore, setting of the gate power, for the portion having a rapid circuit operation to a large value, and setting of the gate power, for the portion having a slow circuit operation, to a small value, cannot be selected during the last wiring process.
Further, in the ECL gate arrays which are known as integrated-circuit (IC) LSI elements, the internal elements are apt to break due to static electricity externally applied via a plurality of input and output terminals. To prevent such an electrostatic breakdown, a circuit for preventing electrostatic breakdown is provided between the external circuit and the input and output terminals.
Such a circuit has a simple construction and is effective. However, if such circuits are provided in the external portions of a plurality of inputs and outputs of the element, the circuit construction of each element becomes large and the cost thereof is increased. Therefore, a circuit for preventing electrostatic breakdown is included in the internal portions of the element. However, an element such as a gate array can be made to have various functions by changing the wiring between each element Therefore, whether each terminal of the gate array is an input terminal or an output terminal depends on which functions are given to the gate array. Further, the construction of a circuit for preventing electrostatic breakdown depends on whether the circuit is used as an input terminal or an output terminal. Therefore, when such circuits are formed so as to correspond to the gate array, two kinds of circuits must be formed depending on whether each circuit is used as an input terminal or an output terminal, and the design must be changed in accordance with the functions of the gate array. This not only increases the manufacturing cost but also considerably decreases the number of different circuits formed in the gate array.
Further, usually, an ECL gate array uses two electric source systems, a high voltage side is called V.sub.cc and a low voltage side is called V.sub.EE. However, the circuit scale becomes large so that electric power dissipation increases. Even in the electric source on the low voltage side, the supply voltage is different at each point. This difference cannot be ignored in some types of circuits.